Logic Design
Logic DesignFocus & Characteristics
FPGA and CPLD design in VHDL
Integration of complex funktions and algorithms Improved performance through parallel processing Flexibility through in-system programming Defined coding styles Custom libraries and IP cores Simulation on register transfer level and gate level Synthesis and implementation on Devices from the manufactureres Xilinx, Lattice, Altera and Actel Design Flow
Specification
Design capture: VHDL code according to coding style and project structure XEMACs as editor and support for project management, makefile creation, code beautifier, linting Version management via Subversion Core integration via IP core and vendor integration via technology library Documentation extraction with vhdldoc Simulation: Build environment with CYGWIN & makefiles Simulation via Modelsim Automatic evaluation of results (for regression tests) Flow prepared for back-annotation Synthesis using the vendor tools Technologies Use of standardized interface for internal buses: Wishbone, Avalon, etc. Encapsulation of funktions regarding reusability IP cores: IICbus, PCI, SPI, CAN, UART, DDR SDRAM controller High-speed serial links (LVDS, Gigabit links, etc.) Implementation of various encoding and compression methods Overview of used components
Tools
Mentor Modelsim PE 6.1
Xilinx ISE from version 7.1 Lattice ispLever from version 5.1 incl. Synplicity Synplify Altera Quartus from version 5.1 Actel Libero IDE |
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